Chiplet Summit, the largest conference fully dedicated to chiplet technologies, has announced the keynote lineup for its fourth annual edition, set to take place February 17–19 at the Santa Clara Convention Center, and the scale and ambition this year feel noticeably bigger. Chiplet Summit 2026 is positioning itself as the industry’s most concentrated meeting point for multi-die design, AI acceleration, and open chiplet ecosystems, pulling together the companies and standards bodies that are quietly redefining how modern silicon is built. The framing is clear: chiplets are no longer a clever workaround for Moore’s Law limits, they are becoming the default architectural language for high-performance computing, AI, and cloud infrastructure. Chuck Sobey, General Chair of the event, summed it up succinctly, noting that the keynotes for the largest Chiplet Summit yet will focus on how chiplets are actively reshaping the semiconductor industry rather than merely promising to do so someday.
The Wednesday keynote program leans heavily into design automation, interoperability, and the practical realities of making multi-die systems work at scale. Abhijeet Chakraborty of Synopsys will explore how AI-driven automation is being applied to multi-die and 3D heterogeneous integration, an area where complexity has traditionally outpaced tooling and human intuition. Letizia Giuliano from Alphawave Semi will trace the evolution of chiplets from early adoption phases into mainstream, system-level deployments, focusing on scalable and interoperable architectures rather than bespoke one-off designs. Juan C. Rey of Siemens EDA is expected to tackle the performance bottlenecks that still plague 3D ICs, introducing AI-assisted methods to speed up design convergence and reduce spiraling costs, a topic that resonates strongly as tape-out budgets keep climbing. Rounding out the day, Debendra Das Sharma, board member of UCIe and one of its co-inventors, will focus on the rapid progress of chiplet interconnect standards and how they are enabling truly modular, mix-and-match silicon ecosystems instead of vendor-locked stacks.
Thursday’s keynotes shift the lens toward deployment, infrastructure, and the economic realities of AI at scale, especially power and cost. David Glasco from Cadence will present modular multi-die approaches aimed at AI, edge computing, and emerging physical AI applications, highlighting how soft IP and hardware-software co-design are becoming inseparable. Imran Yusuf of Arm will examine how chiplet-based infrastructure is enabling more flexible and efficient AI and cloud systems, a critical point as hyperscalers push for customization without exploding development cycles. Cliff Grossner of the Open Compute Project, joined by Anu Ramamurthy from Microchip Technology, will look ahead to the next wave of AI inference, emphasizing low-cost, interoperable chiplet ecosystems designed for both cloud and edge environments, not just flagship datacenters. The keynote slate concludes with Jim Rogers of Marvell, who will address how innovations in chiplet-based memory, connectivity, 3D packaging, and integrated optics are being marshaled to confront one of AI’s most stubborn constraints: power consumption inside hyperscale datacenters, where every watt now has strategic implications.
Taken together, the keynote program makes a quiet but firm statement. Chiplet Summit 2026 is less about evangelizing chiplets as a concept and more about operationalizing them across AI, cloud, and edge systems under real-world constraints. The emphasis on standards, AI-assisted design, interoperability, and power efficiency suggests an industry that has moved past experimentation and is now wrestling with execution, scale, and economics. Santa Clara in February looks set to become a checkpoint for where chiplets stand today, and a preview of how silicon itself will be assembled in the years just ahead, slightly messy, deeply complex, and increasingly modular.