The keynote hall at San Francisco’s Moscone Center filled early on Thursday morning. Advancing AI 2026 had opened the day before with the technical sessions and the developer track, but the second day was the one the industry had cleared its calendar for: two hours, a 9:30 Pacific start, and Lisa Su walking a packed room through the silicon AMD has been promising since this same event a year ago.
Last July the company showed a rendering of a rack called Helios and asked the audience to take it on faith. This July the rack was real, in production, and shipping at the end of the quarter.
The rack takes the stage
Su spent the opening stretch on Helios itself, and the framing was deliberate. This is not an accelerator that slots into an existing chassis. It is AMD’s first rack-scale system, fusing Instinct MI455X GPUs, sixth-generation EPYC “Venice” processors and Pensando DPUs into a scale-up architecture where the entire rack behaves as one machine. It is the direct answer to NVIDIA’s NVL72, and AMD did not pretend otherwise.
The numbers arrived quickly. Thirty-one terabytes of HBM4 across the rack. Roughly fifteen percent more compute and fifty percent more memory bandwidth than the competing system, by AMD’s own accounting. Each MI455X carrying 432 gigabytes of HBM4 across sixteen stacks at 19.6 terabytes per second.
The detail that drew attention from the infrastructure people in the room was quieter than any of those figures. HBM4 in this implementation runs on a 2,048-bit routing interposer, twice the width of the HBM3e layout it replaces. That is how the bandwidth arrives without a matching jump in power draw. It is also why an MI455X card will never find a home in an NVIDIA server, and why NVIDIA’s HBM3e hardware cannot take one. A data center that says yes to Helios is not buying components. It is picking a side.
Venice, and a process lead
The CPU half of the rack got its own segment. EPYC Venice is the first x86 server processor manufactured on TSMC’s 2-nanometer node, scaling to 256 cores and 512 threads, and AMD positioned it three ways at once: as the host processor inside Helios, as a platform for agentic workloads, and as a conventional general-purpose server part for buyers who are not in the AI infrastructure conversation at all.
The subtext was competitive timing. Intel’s P-core Xeon answer is still about a year out. For enterprise teams sitting on a refresh decision, that gap is the whole argument.
AMD also used the morning to launch the MI350P, an air-cooled enterprise accelerator supporting models up to 260 billion parameters, pitched at organizations that want inference capacity without rebuilding their cooling infrastructure. The MI430X for FP64-heavy scientific and sovereign workloads and the MI440X for on-premises enterprise deployment filled out the range, and the MI500 series was previewed without detail.
The guests
Then the stage began to turn over, and the second half of the keynote became the more interesting one.
Meta came first. The company is a lead partner on both Venice and the MI450 generation, with plans for up to six gigawatts of AMD infrastructure and a co-designed accelerator of its own. Meta’s infrastructure leadership made the case that compute, networking, memory, power, cooling and software can no longer be selected separately and assembled at the end. The engineering conversation has to start years ahead of deployment, which in practice means the systems being specified on that stage were aimed at 2028.
OpenAI followed, its representative welcomed on by AMD’s AI group leadership. OpenAI has had Helios hardware for several months already, working alongside AMD engineers on GPT-class workloads across ROCm, networking, compilers, workload debugging and the Triton and Gluon programming tools. The relationship runs in both directions: OpenAI has been feeding AMD data on shifting model requirements and infrastructure bottlenecks, and that feedback shaped the MI400 generation. Its commitment runs to six gigawatts, backed by the warrant structure disclosed last October that lets OpenAI acquire up to 160 million AMD shares at a cent apiece as deployment milestones vest through 2030.
Between them, Meta and OpenAI now represent twelve gigawatts of committed accelerator demand.
Anthropic is preparing up to two gigawatts of MI455X capacity under a multiyear engineering agreement, using Claude to optimize workloads and support ROCm development while AMD runs the model inside parts of its own engineering organization. Microsoft Azure and Oracle were named as early Helios customers, with Oracle expected to be the first public cloud to sell a commercially available supercluster built on 50,000 MI450-class GPUs, starting this quarter.
AT&T brought something different: OTel 2.0, an open-source telecommunications AI model trained on AMD hardware, and a candid account of managing token costs at scale by staying on open models and refusing to standardize on a single vendor’s chips.
The Cerebras moment
The most technically striking segment was also the shortest. Su brought out Andrew Feldman of Cerebras to talk about the part of the inference market that cares less about aggregate throughput than about latency for a smaller number of users.
What the two companies described was a split architecture. Helios handles prompt processing and long context windows. The Cerebras wafer-scale engine handles token generation. The prefill stage is throughput-bound; the decode stage is memory-bandwidth-bound; the two have different optimal hardware, and until now nobody had shipped a product that acknowledged it across vendor lines.
Disaggregated inference has been a conference-paper topic for two years. Watching two competing architectures agree to divide a single request between them was the moment the keynote stopped feeling like a product launch and started feeling like a description of where the market is going.
The software question nobody resolved
ROCm got its segment, and AMD knows it is the weak flank. The company introduced ROCm AI, an agentic platform that generates and optimizes GPU kernels with model assistance rather than requiring hand-tuning, and cited a 3.5x improvement from ROCm 7 alongside functional coverage in the ninety to ninety-five percent range against CUDA.
Those are keynote numbers. Whether they survive contact with independent benchmarks is the story of the next several quarters, not of Thursday morning.
Leaving Moscone
AMD traded near $553 across the two days, more than double where it opened the year, with sell-side targets migrating into the $600s and $700s. First-quarter revenue landed around $10.25 billion, up roughly 38 percent, and the June quarter reports on August 4 against a consensus that assumes a very large jump.
The gigawatt commitments are real and they are also mostly in the future. Helios ships at the end of this quarter and ramps through the next. Between now and then the binding constraint is not demand and it is not design. It is HBM4 supply, which remains the tightest link in the entire chain, and which no keynote can loosen.