FMS: the Future of Memory and Storage opened Tuesday at the Santa Clara Convention Center and runs through Thursday, marking the conference’s twentieth year. The industry that gathered for the first Flash Memory Summit in 2006 was arguing about whether NAND would displace hard drives in the data center. This year it is arguing about something narrower and more consequential: what goes in the gap between the small, expensive pool of high bandwidth memory attached to an AI accelerator and the vast, slow storage sitting behind it.
Every major supplier came to Santa Clara with an answer. The answers do not agree with each other, and most of them cannot coexist in the same server.
Answer one: put flash on the accelerator package
SanDisk and SK hynix moved first, releasing the initial technical specification for High Bandwidth Flash through the Open Compute Project on the day before the show floor opened. The spec covers 8-high and 16-high TSV-stacked NAND assemblies reaching 512GB per device, connected over UCIe, in three performance grades running from roughly 0.4 to 3.0 terabytes per second. The top grade lands in the same band as an HBM4 stack.
The consortium detail matters more than the numbers. Google and Tenstorrent joined during the standardization work, which means the spec has at least one hyperscaler and one accelerator designer attached to it rather than being two memory vendors talking to themselves. A Thursday panel titled around breaking the memory wall pairs SanDisk and SK hynix representatives with a Google DeepMind engineer, which is the first substantial public airing of HBF alongside someone who would actually have to use it.
The constraint on this approach is written into the technology. Flash writes are slow and endurance is finite, so HBF works for inference, where model weights are static, and not for training, where they change constantly. Every HBF discussion at the show framed it that way.
Answer two: put the memory on top of the processor
Samsung’s opening keynote went further and proposed rearranging the package entirely. Its zHBM concept stacks HBM vertically above the AI accelerator rather than placing it alongside on an interposer, cutting the distance data travels to the gap between two bonded wafers. Samsung claims roughly eight times the performance of HBM5, more than ten times the density, three times the energy efficiency and less than half the thermal resistance, with a customer-configurable interlayer between memory and accelerator.
Two things are worth holding onto here. The comparisons are against HBM5, which does not exist as a shipping specification, so this is one concept measured against another. And the thermal resistance claim is the honest one: heat is the reason memory has always sat beside the processor rather than on top of it, and Samsung leading with that number is an admission of where the difficulty lives. No production date was offered.
Samsung also has the only credible path to building such a thing, being the sole supplier that can quote memory, foundry and advanced packaging on the same purchase order. The closing section of its announcement, about one-stop turnkey solutions, is arguably the real message. zHBM is a foundry pitch wearing a memory badge.
Answer three: leave flash where it is and make it faster
Kioxia took the least exotic route and won the show’s Best of Show award in Specialized Storage for it. The GP1 keeps flash at the end of a PCIe 6.0 link and optimises for access rate instead of bandwidth: up to 10 million random read IOPS at 512-byte granularity, latency under five microseconds, built on XL-FLASH generation 2, with a stated path toward 100 million IOPS in later generations. Evaluation samples reach selected customers by the end of this year.
Ten million 512-byte reads per second amounts to only about five gigabytes per second of actual data movement, a fraction of what the link can carry. That is deliberate. The GP1 targets scattered small reads: key-value cache offload, embedding lookups, vector index traversal. Those workloads are limited by how many independent accesses complete per second, not by throughput. It is roughly the position Intel’s Optane occupied before it was discontinued in 2022, and Kioxia’s drive exceeds Optane comfortably on both metrics.
Kioxia is hedging rather than committing. It also brought the XL1, a CXL-attached memory expansion module using XL-FLASH with samples shipping to ecosystem partners this month, and the CM10, announced 30 July as the first enterprise SSD on its 332-layer BiCS generation 10 TLC with an option for direct cold-plate liquid cooling. On-package, on the memory bus, and at the end of PCIe: three positions, one supplier.
The quiet story is wafer bonding
Underneath the architectural argument, a single process technology is doing most of the work. Samsung’s V10 BV-NAND crosses 400 layers using wafer bonding to stack the cells, raising density about 58% over the V9 generation. Kioxia’s generation 10 BiCS uses CMOS directly bonded to array. HBF depends on through-silicon vias and hybrid bonding. SK hynix showed a tenth-generation 375-layer 4D NAND claiming 2.5 times the performance per watt of its predecessor, with enterprise SSDs built on it entering mass production early next year.
Four companies, four product categories, one shared dependency on advanced packaging. That is a meaningful shift in where memory value sits and which suppliers constrain it, and it received far less stage time than the concept models.
The unasked question
All three memory majors are expanding HBM capacity hard, with Samsung targeting something near a 50% increase this year. TrendForce’s framing of 2026 through 2028 as a structural supercycle rests on the observation that HBM4’s 2,048-bit interface and the complexity of advanced NAND stacking limit global bit growth even as capital investment rises. Supply constraint and record investment at the same time is an unusual combination, and it is what makes every announcement at this show read as urgent.
The most useful session on Tuesday was the one nobody quoted in a press release. Jim Handy of Objective Analysis addressed what happens when hyperscaler AI spending moderates, and how previous semiconductor cycles suggest the market repositions once an HBM-first architecture runs into cost or supply limits. That question sits underneath every product on the floor. Four architectures are competing for a tier that only exists because HBM is scarce and expensive. If HBM capacity expansion outruns demand, or if inference economics shift, the tier itself becomes optional.
Nothing announced this week ships in volume before 2027. What ships now is NAND: 400-plus layers at Samsung, 375 at SK hynix, 332 at Kioxia, all of it bonded rather than merely stacked. The concept models will be re-announced next August. The density gains will show up in bit supply and contract pricing within two quarters.