The fourth quarter carries the heaviest concentration of technical disclosure in the semiconductor calendar. Device results that will define the following year’s roadmaps are presented in December, infrastructure specifications are ratified in October, and the equipment order book for the coming year is negotiated in the exhibition halls between them. What follows is the Q4 2026 schedule, with a note on what each event is actually useful for.
Dates are as published by organisers and are worth reconfirming before booking, since venue and date changes are not rare in this calendar.
International Test Conference (ITC 2026)
Date: October 11 to 16, 2026
Location: San Antonio, Texas
Host: IEEE
The primary forum for test and design-for-test, which is a larger cost centre than most outside the industry appreciate. Test time per die is a direct gross margin input, and the pressure has intensified with chiplet architectures, where known-good-die screening has to happen before assembly rather than after.
Useful for anyone tracking test equipment demand, which historically leads and lags fab equipment orders on a different cycle.
2026 OCP Global Summit
Date: October 12 to 15, 2026
Location: San Jose, California
Host: Open Compute Project Foundation
The venue where hyperscaler infrastructure requirements become public specifications. Rack power delivery, liquid cooling standards, optical interconnect and increasingly memory tiering all get worked out here in a form that suppliers then build against.
For memory specifically, OCP has become the place where the tier between HBM and conventional flash is being defined. Specifications ratified at this event tend to appear in product roadmaps twelve to eighteen months later, which makes it a leading indicator rather than a product launch venue.
SEMICON West 2026
Date: October 13 to 15, 2026
Location: San Francisco, California
Host: SEMI
The North American equipment and materials show. Less about technical disclosure than about commercial signalling: capacity announcements, tool introductions, materials supply agreements and the market outlook presentations that set expectations for the following year’s wafer fab equipment spend.
The exhibition floor is the information channel here, not the keynote stage.
International Workshop on Nitride Semiconductors (IWN 2026)
Date: November 8 to 13, 2026
Location: Kumamoto, Japan
GaN and related compound semiconductor research. Relevant to power delivery in data centres, where the shift toward higher voltage distribution to the rack is pulling wide-bandgap devices into infrastructure that used to be silicon’s uncontested territory.
Kumamoto as a venue is not incidental. The prefecture has become a focal point of Japanese fab investment, and the surrounding supply chain build-out is visible from the conference.
SC26
Date: November 15 to 20, 2026
Location: McCormick Place, Chicago, Illinois
The supercomputing conference, and by now the largest single gathering of AI infrastructure buyers in the calendar. The TOP500 list update, interconnect announcements, cooling deployments at scale and the procurement conversations that accompany national laboratory awards.
For memory and storage vendors, SC is where bandwidth-per-watt claims meet customers who measure them.
SEMICON Japan 2026
Date: December 9 to 11, 2026
Location: Tokyo Big Sight, Tokyo
Host: SEMI
The Japanese equipment, materials and packaging show, with co-located summits on advanced packaging and chiplets, design innovation, and metrology and inspection.
Japan’s position in materials and in NAND makes this the most relevant single event for anyone tracking the flash supply side, and the packaging summits have grown in importance as advanced packaging has become the actual bottleneck in AI accelerator supply.
IEDM 2026
Date: December 12 to 16, 2026
Location: Hilton San Francisco Union Square, San Francisco, California
Host: IEEE Electron Devices Society
The seventy-second annual International Electron Devices Meeting, and the most consequential technical event of the quarter. Device physics, process technology, memory cell architecture, power devices and emerging computing structures. This is where the transistor and memory cell results that define the next node generation are formally disclosed.
Late news submissions open in August, which means the most significant results are frequently not visible in the advance program. Anyone reading the preliminary agenda in October and concluding the year is quiet has read the wrong document.
How to read the quarter
October is commercial. The specifications and the order book conversations happen at OCP and SEMICON West, and the signals are about volume and timing.
December is technical. IEDM and SEMICON Japan land within days of each other and produce the disclosures that set the following year’s expectations for density, bandwidth and yield.
November sits between them and belongs to the buyers. SC is the only event of the three where the people writing the cheques outnumber the people writing the papers.