Registration has opened for the 2026 International Compact Modeling Conference, a focused gathering that sits right at the intersection of device physics, circuit behavior, and the increasingly unforgiving realities of advanced semiconductor scaling. Hosted aboard the historic RMS Queen Mary in Long Beach, the setting alone feels slightly surreal—old-world engineering wrapped around discussions of nanometer-scale abstraction and model fidelity.
Organized by Silicon Integration Initiative in partnership with IEEE and the IEEE Electron Devices Society, ICMC 2026 keeps its scope deliberately tight. This is not a broad semiconductor expo; it’s a working forum for people who care about how transistors behave when you actually try to model them—how equations meet silicon, and where they start to break.
The conference runs for two days, built around keynote talks, invited presentations, and technical sessions that dive into compact modeling techniques, circuit simulation accuracy, and process-aware modeling challenges. In practice, that means discussions that often sit somewhere between physics papers and engineering pragmatism—threshold voltages that don’t behave, variability that refuses to average out, and models that need to be both simple enough to simulate and precise enough to matter.
Keynotes anchor the program with a lineup that reflects the field’s intellectual backbone. Chenming Hu, known for foundational work in MOSFET modeling, brings historical depth and forward-looking perspective. Elyse Rosenbaum contributes expertise in reliability and device degradation—topics that have quietly become central as scaling pushes materials harder than ever. Yuan Taur, whose work shaped modern device theory, rounds out a trio that signals the conference’s emphasis on fundamentals rather than hype.
Beyond the sessions, the structure is intentionally social in a low-key, technical way. Coffee breaks, a shared lunch, and an evening reception are built into the schedule—not as filler, but as the actual connective tissue of this kind of event. Compact modeling is a niche where conversations often continue in hallways, over diagrams sketched on napkins or laptops opened mid-discussion. You can almost picture someone arguing about short-channel effects while staring out at the harbor.
There’s also a practical edge to the timing. With continued pressure on semiconductor design cycles, tighter integration between EDA tools and physical models, and the creeping complexity of new device architectures, compact modeling is having one of those moments where it becomes more visible—less of a background discipline, more of a bottleneck or enabler depending on how well it’s done.
Early registration comes with a small discount, but realistically the value here isn’t in the price difference—it’s in the density of expertise in one place, for a very specific problem space that most broader conferences only skim.