WHERE: ETH Zurich, Gloriastrasse 35, CH 8092 Zurich, Switzerland
WHEN: Tuesday, June 11 to Thursday, June 13, 2019
WHAT: The RISC-V Workshop Zurich will showcase the open, expansive and international RISC-V ecosystem. The event will highlight current and prospective projects and implementations that influence the future evolution of the free and open RISC-V instruction set architecture (ISA), with a focus on the momentum and growth of the RISC-V Foundation across Europe and beyond.
The event will feature two full days of presentations and updates on the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more. RISC-V Foundation members presenting at the Workshop include: AdaCore, CEA, CloudBEAR, Dover Microsystems, Draper Labs, Embecosm, ETH Zurich, Hex Five Security, Huawei, Microchip Technology, OneSpin Solutions, Princeton University, Qamcom Research & Technology, Rambus, SiFive, Syntacore and Western Digital. The third day of the event will feature meetings for RISC-V Foundation members.
Tuesday, June 11, 2019:
Guiding the Future of RISC-V
When: 9:00 – 09:15 CEST
Who: Calista Redmond, RISC-V Foundation
Energy Efficient Computing from Exascale to MicroWatts: The RISC-V Playground
When: 9:15 – 09:40 CEST
Who: Luca Benini, ETH Zurich
RISC-V State of the Union
When: 9:40 – 10:05 CEST
Who: Krste Asanovic, UC Berkeley and SiFive
RISC-V Technical Committee Update
When: 10:05 – 10:20 CEST
Who: RISC-V Foundation
RISC-V Marketing Committee Update
When: 10:20 – 10:35 CEST
Who: Ted Marena, RISC-V Foundation and Western Digital
OpenPiton+Ariane: The First Linux-Booting Open-Source RISC-V Manycore
When: 11:30 – 11:45 CEST
Who: Jonathan Balkind, Princeton University; Michael Schaffner, ETH Zurich
efabless’ Raven: PicoRV32 on an ASIC, Open Source, Open Silicon
When: 11:45 – 12:00 CEST
Who: Tim Edwards and Mohamed Kassem, efabless Corporation
PULP-NN: An Open-Source Library for Deeply-Embedded and Quantized Neural Networks (QNNs) on a RISC-V Based Parallel Ultra Low Power Cluster
When: 12:00 – 12:15 CEST
Who: Angelo Garofalo, University of Bologna; Luca Benini, ETH Zurich
Bit by bit – How to fit 8 RISC-V Cores in a $38 FPGA board
When: 12:15 – 12:30 CEST
Who: Olof Kindgren, Qamcom Research & Technology
OpenSBI Deep Dive
When: 13:30 – 13:55 CEST
Who: Anup Patel, Western Digital
Secure Bootloader for RISC-V
When: 13:55 – 14:10 CEST
Who: David Garske and Daniele Lacamera, wolfSSL Inc.
An Open Source Approach to System Security
When: 14:10 – 14:25 CEST
Who: Helena Handschuh, RISC-V Foundation and Rambus
60 Second Poster Preview Sessions
When: 14:25 – 14:50 CEST
PolarFire SoC: a Secure, Low Latency Heterogeneous Compute Platform for the Edge
When: 15:20 – 15:45 CEST
Who: Ted Speers, Microchip Technology
CHIPS Alliance – an Open Hardware Group
When: 15:45 – 16:00 CEST
Who: Yunsup Lee, SiFive
PULP Platform: What’s Next?
When: 16:00 – 16:15 CEST
Who: Frank Gürkaynak, ETH Zurich
Bridging the Gap in the RISC-V Memory Models
When: 16:15 – 16:30 CEST
Who: Stefanos Kaxiras, Uppsala University and Eta Scale AB; Alberto Ros, University of Murcia and Eta Scale AB
The First Space-Qualified Klessydra RISC-V Microcontroller to be Launched on a Satellite
When: 16:30 – 16:45 CEST
Who: Mauro Olivieri, Sapienza University of Rome and Barcelona Supercomputing Center; Luigi Blasi and Francesco Vigli, Sapienza University of Rome
What You Simulate is What You Synthesize: Design of a RISC-V Core from C++ Specifications
When: 16:45 – 17:00 CEST
Who: Simon Rokicki and Olivier Sentieys, INRIA
Updates from RISC-V Foundation Working Groups
When: 17:00 – 18:00 CEST
Who: RISC-V Foundation
Wednesday, June 12, 2019:
RISC-V Software State of the Union
When: 9:25 – 09:50 CEST
Who: Palmer Dabbelt, SiFive
Open Source Compiler Tool Chains for RISC-V
When: 9:50 – 10:15 CEST
Who: Jeremy Bennett, Embecosm
Enabling RISC-V Development with QEMU
When: 10:15 – 10:30 CEST
Who: Alistair Francis, Western Digital
Building Better Soft RISC-V IP Cores through Mi-V Verification and Compliance Testing
When: 11:00 – 11:25 CEST
Who: Stuart Hoad, Microchip Technology
Embench TM: A Free Benchmark Suite for Embedded Computing from an Academic-Industry Cooperative (Towards the Long Overdue and Deserved Demise of Dhrystone)
When: 11:25 – 11:50 CEST
Who: David Patterson, RISC-V Foundation; Jeremy Bennett, Embecosm
Developing with FreeRTOS and RISC-V
When: 11:50 – 12:15 CEST
Who: Richard Barry, AWS
Enable RISC-V Capability in Cloud Computing
When: 12:15 – 12:30 CEST
Who: Zhipeng Huang, Huawei
SweRV (RISC-V) Debug, Trace and On-Chip Analytics for SOC
When: 13:30 – 13:45 CEST
Who: Sesibhushana Rao Bommana and Mukesh Panda, Western Digital
TestRIG: Using RVFI-DII to Eliminate the “Test Gap” Between Specification and Implementation
When: 13:45 – 14:00 CEST
Who: Jonathan Woodruff, University of Cambridge
Formal Verification of PULPino and Other RISC-V SoCs
When: 14:00 – 14:15 CEST
Who: Nicolae Tusinchi and Sven Beyer, OneSpin Solutions
Ada & PolarFire SoC, a Software and Hardware Alloy for Safety & Security
When: 14:15 – 14:30 CEST
Who: Fabien Chouteau, AdaCore; Pierre Selwan, Microsemi, a Microchip company
Building Secure Systems using RISC-V and Rust
When: 14:30 – 14:45 CEST
Who: Arun Thomas, Draper Labs
60 Second Poster Preview Sessions
When: 14:45 – 15:15 CEST
An Open-Source API Proposal for a Multi-Domain RISC-V Trusted Execution Environment
When: 15:45 – 16:10 CEST
Who: Cesare Garlati, Hex Five Security
Protecting RISC-V Processors Against Physical Attacks
When: 16:10 – 16:25 CEST
Who: Mario Werner, Graz University of Technology
A Security Policy Definition Language, Semantics, and Open Source Tools
When: 16:25 – 16:40 CEST
Who: Greg Sullivan, Dover Microsystems; Chris Casinghino, Draper Labs
An Intrinsically Secure RISC V processor
When: 16:40 – 16:55 CEST
Who: Olivier Savry, CEA
SiFive 7-Series RISC-V Core IP Enables Embedded Intelligence
When: 16:55 – 17:10 CEST
Who: Yunsup Lee, SiFive
CloudBEAR RISC-V Processor IP Product Line
When: 17:10 – 17:25 CEST
Who: Alexander Kozlov, CloudBEAR
Syntacore 64bit RISC-V Core IP Product Line
When: 17:25 – 17:40 CEST
Who: Alexander Redkin and Dmitry Gusev, Syntacore
Configurable LLDB Debuggers for RISC-V
When: 17:40 – 17:55 CEST
Who: To be announced
To register for the event, please visit: https://tmt.knect365.com/risc-v-workshop-zurich/purchase/select-package. To learn more about sponsorship opportunities, please visit: https://tmt.knect365.com/risc-v-workshop-zurich/sponsor.
For press interested in attending, please email: [email protected] to receive your complimentary pass. To learn more about the RISC-V Foundation, its free and open architecture, and membership information, please visit: https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
Additional Information
RISC-V and Open POWER Instruction Set Architecture (ISA) Fortunes are Rising, Market Analysis